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ds97z8x1500 p r e l i m i n a r y 1 1 p reliminary p roduct s pecification z86e33/733/e34 Z86E43/743/e44 1 cmos z8 otp m icrocontrollers features n standard temperature (v cc = 3.5v to 5.5v) n extended temperature (v cc = 4.5v to 5.5v) n available packages: 28-pin dip/soic/plcc otp (e33/733/e34) 40-pin dip otp (e43/743/e44) 44-pin plcc/qfp otp (e43/743/e44) n software enabled watch-dog timer (wdt) n push-pull/open-drain programmable on port 0, port 1, and port 2 n 24/32 input/output lines n clock-free wdt reset n auto power-on reset (por) n programmable otp options: rc oscillator eprom protect auto latch disable permanently enabled wdt crystal oscillator feedback resistor disable ram protect n low-power consumption: 60 mw n fast instruction pointer: 0.75 m s n two standby modes: stop and halt n digital inputs cmos levels, schmitt-triggered n software programmable low emi mode n two programmable 8-bit counter/timers each with a 6-bit programmable prescaler n six vectored, priority interrupts from six different sources n two comparators n on-chip oscillator that accepts a crystal, ceramic resonator, lc, rc, or external clock drive general description the z86e33/733/e34/e43/743/e44 8-bit one-time pro- grammable (otp) microcontrollers are members of zilog's single-chip z8 ? mcu family featuring enhanced wake-up circuitry, programmable watch-dog timers, low noise emi options, and easy hardware/software system expan- sion capability. four basic address spaces support a wide range of mem- ory configurations. the designer has access to three addi- tional control registers that allow easy access to register mapped peripheral and i/o circuits. for applications demanding powerful i/o capabilities, the z86e33/733/e34 have 24 pins, and the Z86E43/743/e44 have 32 pins of dedicated input and output. these lines are grouped into four ports, eight lines per port, and are config- urable under software control to provide timing, status sig- device rom (kb) ram* (bytes) i/o lines speed (mhz) z86e33 4 237 24 12 z86733 8 237 24 12 z86e34 16 237 24 12 Z86E43 4 236 32 12 z86743 8 236 32 12 z86e44 16 236 32 12 note: *general-purpose
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 2 p r e l i m i n a r y ds97z8x1500 general description (continued) nals, and parallel i/o with or without handshake, and ad- dress/data bus for interfacing external memory. notes: all signals with a preceding front slash, "/", are active low. for example, b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: connection circuit device power v cc v dd ground gnd v ss figure 1. functional block diagram port 3 counter/ timers (2) interrupt control two analog comparators port 2 i/o (bit programmable) alu flags machine timing & instruction control program counter vcc gnd xtal 4 4 port 0 output input address or i/o (nibble programmable) 8 address/data or i/o (byte programmable) /as /ds r//w /reset reset wdt, por port 1 otp register file register pointer (e43/743/e44 only) (e43/743/e44 only)
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 3 1 figure 2. eprom programming block diagram address mux eprom test rom otp options ad 11- 0 z8 mcu address counter pgm + test mode logic epm p32 /ce xt1 /pgm p02 d7 - 0 ad 11- 0 ad 13- 0 data mux z8 port 2 d7 - 0 /oe p31 vpp p33 d7 - 0 clr (p00) clk (p01)
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 4 p r e l i m i n a r y ds97z8x1500 pin identification figure 3. 40-pin dip pin conguration standard mode r//w p25 p26 p27 p04 p05 p06 p14 p15 p07 vcc p16 p17 xtal2 xtal1 p31 p32 p33 p34 /as /ds p24 p23 p22 p21 p20 p03 p13 p12 gnd p02 p11 p10 p01 p00 p30 p36 p37 p35 /reset 40 dip 40 - pin 1 20 21 table 1. 40-pin dip pin identication standard mode pin # symbol function direction 1 r//w read/write output 2-4 p25-p27 port 2, pins 5,6,7 in/output 5-7 p04-p06 port 0, pins 4,5,6 in/output 8-9 p14-p15 port 1, pins 4,5 in/output 10 p07 port 0, pin 7 in/output 11 v cc power supply 12-13 p16-p17 port 1, pins 6,7 in/output 14 xtal2 crystal oscillator output 15 xtal1 crystal oscillator input 16-18 p31-p33 port 3, pins 1,2,3 input 19 p34 port 3, pin 4 output 20 /as address strobe output 21 /reset reset input 22 p35 port 3, pin 5 output 23 p37 port 3, pin 7 output 24 p36 port 3, pin 6 output 25 p30 port 3, pin 0 input 26-27 p00-p01 port 0, pins 0,1 in/output 28-29 p10-p11 port 1, pins 0,1 in/output 30 p02 port 0, pin 2 in/output 31 gnd ground 32-33 p12-p13 port 1, pins 2,3 in/output 34 p03 port 0, pin 3 in/output 35-39 p20-p24 port 2, pins 0,1,2,3,4 in/output 40 /ds data strobe output
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 5 1 figure 4. 44-pin plcc pin conguration standard mode 44-pin plcc 7 17 p21 p22 p23 p24 /ds nc r//w p25 p26 p27 p04 p30 p36 p37 p35 /reset r//rl /as p34 p33 p32 p31
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 6 p r e l i m i n a r y ds97z8x1500 pin identification (continued) figure 5. 44-pin qfp pin conguration standard mode 34 44 p21 p22 p23 p24 /ds nc r//w p25 p26 p27 p04 p30 p36 p37 p35 /reset r//rl /as p34 p33 p32 p31
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 7 1 figure 6. 40-pin dip pin conguration eprom mode nc d5 d6 d7 nc nc nc nc nc nc vcc nc nc nc /ce /oe epm vpp nc nc nc d4 d3 d2 d1 d0 nc nc nc gnd /pgm nc nc clk clr nc nc nc nc nc 40 40-pin dip 1 20 21 table 4. 40-pin dip package pin identication eprom mode pin # symbol function direction 1 nc no connection 2-4 d5-d7 data 5,6,7 in/output 5-10 nc no connection 11 v cc power supply 12-14 nc no connection 15 /ce chip select input 16 /oe output enable input 17 epm eprom prog. mode input 18 vpp prog. voltage input 19-25 nc no connection 26 clr clear input 27 clk clock input 28-29 nc no connection 30 /pgm prog. mode input 31 gnd ground 32-34 nc no connection 35-39 d0-d4 data 0,1,2,3,4 in/output 40 nc no connection
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 8 p r e l i m i n a r y ds97z8x1500 pin identification (continued) figure 7. 44-pin plcc pin conguration eprom programming mode 44 -pin plcc 7 17 d1 d2 d3 d4 nc nc nc d5 d6 d7 nc nc nc nc nc nc nc nc nc vpp epm /oe
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 9 1 figure 8. 44-pin qfp pin conguration eprom programming mode 34 44 d1 d2 d3 d4 nc nc nc d5 d6 d7 nc nc nc nc nc nc nc nc nc vpp epm /oe
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 10 p r e l i m i n a r y ds97z8x1500 pin identification (continued) figure 9. standard mode 28-pin dip/soic pin conguration table 7. 28-pin dip/soic/plcc pin identication standard mode pin # symbol function direction 1-3 p25-p27 port 2, pins 5,6, in/output 4-7 p04-p07 port 0, pins 4,5,6,7 in/output 8 v cc power supply 9 xtal2 crystal oscillator output 10 xtal1 crystal oscillator input 11-13 p31-p33 port 3, pins 1,2,3 input 14-15 p34-p35 port 3, pins 4,5 output 16 p37 port 3, pin 7 output 17 p36 port 3, pin 6 output 18 p30 port 3, pin 0 input 19-21 p00-p02 port 0, pins 0,1,2 in/output 22 v ss ground 23 p03 port 0, pin 3 in/output 24-28 p20-p24 port 2, pins 0,1,2,3,4 in/output p25 p26 p27 p04 p05 p06 p07 vcc xtal2 xtal1 p31 p32 p33 p34 p24 p23 p22 p21 p20 p03 vss p02 p01 p00 p30 p36 p37 p35 28 28-pin dip/soic 1 14 15 figure 10. standard mode 28-pin plcc pin conguration 25 19 5 11 18 12 26 4 28-pin plcc 1 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx p21 p20 p03 vss p02 p01 p00 p05 p06 p07 vcc xt2 xt1 p31
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 11 1 figure 11. eprom programming mode 28-pin dip/soic pin conguration figure 12. eprom programming mode 28-pin plcc pin conguration d5 d6 d7 nc nc nc nc vcc nc /ce /oe epm vpp nc d4 d3 d2 d1 d0 nc vss /pgm clk clr nc nc nc nc 28 28-pin dip/soic 1 14 15 25 19 5 11 18 12 26 4 28-pin plcc 1 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx d1 d0 nc vss /pgm clk clr nc nc nc vcc nc /ce /oe
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 12 p r e l i m i n a r y ds97z8x1500 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; functional operation of the device at any condition above those indicated in the oper- ational sections of these specifications is not implied. ex- posure to absolute maximum rating conditions for an ex- tended period may affect device reliability. total power dissipation should not exceed 1.2 w for the package. power dissipation is calculated as follows: total power dissipation = v dd x [ i dd ?(sum of i oh ) ] + sum of [ (v dd ?v oh ) x i oh ] + sum of (v 0l x i 0l ) standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to ground. positive current flows into the referenced pin (test load). parameter min max units ambient temperature under bias ?0 +105 c storage temperature ?5 +150 c voltage on any pin with respect to v ss [note 1] ?.6 +7 v voltage on v dd pin with respect to v ss ?.3 +7 v voltage on xtal1, p32, p33 and /reset pins with respect to v ss [note 2] ?.6 v dd +1 v total power dissipation 1.21 w maximum allowable current out of v ss 220 ma maximum allowable current into v dd 180 ma maximum allowable current into an input pin [note 3] ?00 +600 m a maximum allowable current into an open-drain pin [note 4] ?00 +600 m a maximum allowable output current sunk by any i/o pin 25 ma maximum allowable output current sourced by any i/o pin 25 ma maximum allowable output current sunk by /reset pin 3 ma notes: 1. this applies to all pins except xtal pins and where otherwise noted. 2. there is no input protection diode from pin to v dd . 3. this excludes xtal pins. 4. device pin is not at an output low state. figure 13. test load diagram 150 pf from output under test
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 13 1 capacitance t a = 25?, v cc = gnd = 0v, f = 1.0 mhz; unmeasured pins returned to gnd. dc electrical characteristics parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf t a = 0 c to +70 c sym parameter v cc note [3] min max typical @ 25? units conditions notes v ch clock input high voltage 3.5v 5.5v 0.7 v cc 0.7 v cc v cc +0.3 v cc +0.3 1.8 2.5 v v driven by external clock generator v cl clock input low voltage 3.5v 5.5v gnd-0.3 gnd-0.3 0.2 v cc 0.2 v cc 0.9 1.5 v v driven by external clock generator v ih input high voltage 3.5v 5.5v 0.7 v cc 0.7 v cc v cc +0.3 v cc +0.3 2.5 2.5 v v v il input low voltage 3.5v 5.5v gnd-0.3 gnd-0.3 0.2 v cc 0.2 v cc 1.5 1.5 v v v oh output high voltage low emi mode 3.5v 5.5v v cc ?.4 v cc -0.4 3.3 4.8 v v i oh = ?0.5 ma v oh1 output high voltage 3.5v 5.5v v cc ?.4 v cc ?.4 3.3 4.8 v v i oh = -2.0 ma i oh = -2.0 ma v ol output low voltage low emi mode 3.5v 5.5v 0.4 0.4 0.2 0.2 v v i ol = +1.0 ma i ol = +1.0 ma v ol1 output low voltage 3.5v 5.5v 0.4 0.4 0.1 0.1 v v i ol = + 4.0 ma i ol = + 4.0 ma 8 8 v ol2 output low voltage 3.5v 5.5v 1.2 1.2 0.5 0.5 v v i ol = + 10 ma i ol = + 10 ma 8 8 v rh reset input high voltage 3.5v 5.5v .8 v cc .8 v cc v cc v cc 1.7 2.1 v v 13 13 v rl reset input low voltage 3.5v 5.5v gnd ?.3 gnd ?.3 0.2 v cc 0.2 v cc 1.3 1.7 v v 13 13 v olr reset output low voltage 3.5v 5.5v 0.6 0.6 0.3 0.2 v v i ol = +1.0 ma i ol = +1.0 ma 13 13 v offset comparator input offset voltage 3.5v 5.5v 25 25 10 10 mv mv v icr input common mode voltage range 3.5v 5.5v 0 0 v cc -1.0v v cc -1.0v v v 10 10 i il input leakage 3.5v 5.5v ? ? 2 2 0.032 0.032 m a m a v in = 0v, v cc v in = 0v, v cc i ol output leakage 3.5v 5.5v ? -1 2 2 0.032 0.032 m a m a v in = 0v, v cc v in = 0v, v cc
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 14 p r e l i m i n a r y ds97z8x1500 dc electrical characteristics (continued) i ir reset input current 3.5v 5.5v ?0 ?0 ?30 ?80 ?5 ?12 m a m a i cc supply current 3.5v 5.5v 15 20 5 15 ma ma @ 12 mhz @ 12 mhz 4,5 4,5 i cc1 standby current halt mode 3.5v 5.5v 4 6 2 4 ma ma v in = 0v, v cc @ 12 mhz 4,5 4,5 3.5v 5.5v 3 5 1.5 3 ma ma clock divide by 16 @ 12 mhz 4,5 4,5 i cc2 standby current stop mode 3.5v 5.5v 3.5v 5.5v 10 10 15 30 2 3 7 10 m a m a m a m a v in = 0v, v cc v in = 0v, v cc v in = 0v, v cc v in = 0v, v cc 6,11 6,11 6,11,14 6,11,14 i all auto latch low current 3.5v 5.5v 0.7 1.4 8 15 2.4 4.7 m a m a 0v Z86E43/743/e44 only. 14. wdt running t a = 0 c to +70 c sym parameter v cc note [3] min max typical @ 25? units conditions notes
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 15 1 t a =?0 c to +105 c sym parameter v cc note [3] min max typical @ 25? units conditions notes v ch clock input high voltage 4.5v 5.5v 0.7 v cc 0.7 v cc v cc +0.3 v cc +0.3 2.5 2.5 v v driven by external clock generator v cl clock input low voltage 4.5v 5.5v gnd-0.3 gnd-0.3 0.2 v cc 0.2 v cc 1.5 1.5 v v driven by external clock generator v ih input high voltage 4.5v 5.5v 0.7 v cc 0.7 v cc v cc +0.3 v cc +0.3 2.5 2.5 v v v il input low voltage 4.5v 5.5v gnd-0.3 gnd-0.3 0.2 v cc 0.2 v cc 1.5 1.5 v v v oh output high voltage low emi mode 4.5v 5.5v v cc ?.4 v cc ?.4 4.8 4.8 v v i oh = ?0.5 ma i oh = ?0.5 ma 8 8 v oh1 output high voltage 4.5v 5.5v v cc ?.4 v cc ?.4 4.8 4.8 v v i oh = -2.0 ma i oh = -2.0 ma 8 8 v ol output low voltage low emi mode 4.5v 5.5v 0.4 0.4 0.2 0.2 v v i ol = +1.0 ma i ol = +1.0 ma v ol1 output low voltage 4.5v 5.5v 0.4 0.4 0.1 0.1 v v i ol = + 4.0 ma i ol = +4.0 ma 8 8 v ol2 output low voltage 4.5v 5.5v 1.2 1.2 0.5 0.5 v v i ol = + 12 ma i ol = + 12 ma 8 8 v rh reset input high voltage 4.5v 5.5v .8 v cc .8 v cc v cc v cc 1.7 2.1 v v 13 13 v olr reset output low voltage 4.5v 5.5v 0.6 0.6 0.3 0.2 v v i ol = +1.0 ma i ol = +1.0 ma 13 13 v offset comparator input offset voltage 4.5v 5.5v 25 25 10 10 mv mv v icr input common mode voltage range 4.5v 5.5v 0 0 v cc -1.5v v cc -1.5v v v 10 10 i il input leakage 4.5v 5.5v ? ? 2 2 <1 <1 m a m a v in = 0v, v cc v in = 0v, v cc i ol output leakage 4.5v 5.5v ? ? 2 2 <1 <1 m a m a v in = 0v, v cc v in = 0v, v cc i ir reset input current 4.5v 5.5v ?8 ?8 ?80 ?80 ?12 ?12 m a m a 13 13 i cc supply current 4.5v 5.5v 20 20 15 15 ma ma @ 12 mhz @ 12 mhz 4,5 4,5 i cc1 standby current halt mode 4.5v 5.5v 6 6 2 4 ma ma v in = 0v, v cc @ 12 mhz v in = 0v, v cc @ 12 mhz 4,5 4,5 i cc2 standby current (stop mode) 4.5v 5.5v 4.5v 5.5v 10 10 40 40 2 3 10 10 m a m a m a m a v in = 0v, v cc v in = 0v, v cc v in = 0v, v cc v in = 0v, v cc 6,11 6,11 6,11,14 6,11,14
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 16 p r e l i m i n a r y ds97z8x1500 dc electrical characteristics (continued) i all auto latch low current 4.5v 5.5v 1.4 1.4 20 20 4.7 4.7 m a m a 0v < v in < v cc 0v < v in < v cc 9 9 i alh auto latch high current 4.5v 5.5v ?.0 ?.0 ?0 ?0 ?.8 ?.8 m a m a 0v < v in < v cc 0v < v in < v cc 9 9 t por power on reset 4.5v 5.5v 2.0 2.0 14 14 4 4 ms ms v lv auto reset voltage 2.0 3.3 2.8 v 1 1. device does function down to the auto reset voltage. 2. gnd=0v 3. the v cc voltage specification of 5.5v guarantees 5.0v ?0.5v. 4. all outputs unloaded, i/o pins floating, inputs at rail. 5. cl1= cl2 = 22 pf 6. same as note [4] except inputs at v cc . 7. maximum temperature is 70? 8. std mode (not low emi mode) 9. auto latch (mask option) selected 10. for analog comparator inputs when analog comparators are enabled. 11. clock must be forced low, when xtal1 is clock driven and xtal2 is floating. 12. typicals are at v cc = 5.0v 13. Z86E43/743/e44 only. 14. wdt is not running. t a =?0 c to +105 c sym parameter v cc note [3] min max typical @ 25? units conditions notes
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 17 1 figure 14. external i/o or memory read/write timing (Z86E43/743/e44 only) r//w , /dm 9 12 18 3 16 13 4 5 8 1 1 6 17 10 15 7 14 2 1 port 0 port 1 /as /ds (read) port1 /ds (w rite) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0 19
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 18 p r e l i m i n a r y ds97z8x1500 dc electrical characteristics (continued) t a = 0 c to 70 c 12 mhz no symbol parameter note [3] v cc min max units notes 1 tda(as) address valid to /as rise delay 3.5v 5.5v 35 35 ns ns 2 2 2 tdas(a) /as rise to address float delay 3.5v 5.5v 45 45 ns ns 2 2 3 tdas(dr) /as rise to read data reqd valid 3.5v 5.5v 250 250 ns ns 1,2 1,2 4 twas /as low width 3.5v 5.5v 55 55 ns ns 2 2 5 tdas(ds) address float to /ds fall 3.5v 5.5v 0 0 ns ns 6 twdsr /ds (read) low width 3.5v 5.5v 200 200 ns ns 1,2 1,2 7 twdsw /ds (write) low width 3.5v 5.5v 110 110 ns ns 1,2 1,2 8 tddsr(dr) /ds fall to read data req? valid 3.5v 5.5v 150 150 ns ns 1,2 1,2 9 thdr(ds) read data to /ds rise hold time 3.5v 5.5v 0 0 ns ns 2 2 10 tdds(a) /ds rise to address active delay 3.5v 5.5v 45 55 ns ns 2 2 11 tdds(as) /ds rise to /as fall delay 3.5v 5.5v 30 45 ns ns 2 2 12 tdr/w(as) r//w valid to /as rise delay 3.5v 5.5v 45 45 ns ns 2 2 13 tdds(r/w) /ds rise to r//w not valid 3.5v 5.5v 45 45 ns ns 2 2 14 tddw(dsw) write data valid to /ds fall (write) delay 3.5v 5.5v 55 55 ns ns 2 2 15 tdds(dw) /ds rise to write data not valid delay 3.5v 5.5v 45 55 ns ns 2 2 16 tda(dr) address valid to read data reqd valid 3.5v 5.5v 310 310 ns ns 1,2 1,2 17 tdas(ds) /as rise to /ds fall delay 3.5v 5.5v 65 65 ns ns 2 2 18 tddm(as) /dm valid to /as rise delay 3.5v 5.5v 35 35 ns ns 2 2 19 thds(as) /ds valid to address valid hold time 3.5v 5.5v 35 35 ns ns 2 2 notes: 1. when using extended memory timing, add 2 tpc. 2. timing numbers given are for minimum tpc. 3. the v cc voltage specification of 5.5v guarantees 5.0v ?.5v and the v cc voltage specification of 3.5v guarantees only 3.5v standard test load all timing references use 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. for standard mode (not low-emi mode for outputs) with smr d1 = 0, d0 = 0.
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 19 1 t a = -40 c to 105 c 12 mhz no symbol parameter note [3] v cc min max units notes 1 tda(as) address valid to /as rise delay 4.5v 5.5v 35 35 ns ns 2 2 2 tdas(a) /as rise to address float delay 4.5v 5.5v 45 45 ns ns 2 2 3 tdas(dr) /as rise to read data reqd valid 4.5v 5.5v 250 250 ns ns 1,2 1,2 4 twas /as low width 4.5v 5.5v 55 55 ns ns 2 2 5 tdas(ds) address float to /ds fall 4.5v 5.5v 0 0 ns ns 6 twdsr /ds (read) low width 4.5v 5.5v 200 200 ns ns 1,2 1,2 7 twdsw /ds (write) low width 4.5v 5.5v 110 110 ns ns 1,2 1,2 8 tddsr(dr) /ds fall to read data req? valid 4.5v 5.5v 150 150 ns ns 1,2 1,2 9 thdr(ds) read data to /ds rise hold time 4.5v 5.5v 0 0 ns ns 2 2 10 tdds(a) /ds rise to address active delay 4.5v 5.5v 45 55 ns ns 2 2 11 tdds(as) /ds rise to /as fall delay 4.5v 5.5v 45 45 ns ns 2 2 12 tdr/w(as) r//w valid to /as rise delay 4.5v 5.5v 45 45 ns ns 2 2 13 tdds(r/w) /ds rise to r//w not valid 4.5v 5.5v 45 45 ns ns 2 2 14 tddw(dsw) write data valid to /ds fall (write) delay 4.5v 5.5v 55 55 ns ns 2 2 15 tdds(dw) /ds rise to write data not valid delay 4.5v 5.5v 55 55 ns ns 2 2 16 tda(dr) address valid to read data reqd valid 4.5v 5.5v 310 310 ns ns 1,2 1,2 17 tdas(ds) /as rise to /ds fall delay 4.5v 5.5v 65 65 ns ns 2 2 18 tddm(as) /dm valid to /as rise delay 4.5v 5.5v 35 35 ns ns 2 2 19 thds(as) /ds valid to address valid hold time 4.5v 5.5v 35 35 ns ns 2 2 notes: 1. when using extended memory timing, add 2 tpc. 2. timing numbers given are for minimum tpc. 3. the v cc voltage specification of 5.5v guarantees 5.0v ?0.5v and the v cc voltage specification of 3.5v guarantees only 3.5v standard test load all timing references use 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. for standard mode (not low-emi mode for outputs) with smr, d1 = 0, d0 = 0.
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 20 p r e l i m i n a r y ds97z8x1500 dc electrical characteristics (continued) figure 15. additional timing diagram clock 1 3 4 8 2 2 3 tin irqn 6 5 7 7 11 clock setup 10 9 stop mode recovery source
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 21 1 additional timing table (divide-by-one mode) t a = 0 c to +70 c 4 mhz 6 mhz no symbol parameter v cc note [6] min max min max units notes 1 tpc input clock period 3.5v 5.5v 250 250 dc dc 166 166 dc dc ns ns 1,7,8 1,7,8 2 trc,tfc clock input rise & fall times 3.5v 5.5v 25 25 25 25 ns ns 1,7,8 1,7,8 3 twc input clock width 3.5v 5.5v 100 100 100 100 ns ns 1,7,8 1,7,8 4 twtinl timer input low width 3.5v 5.5v 100 70 100 70 ns ns 1,7,8 1,7,8 5 twtinh timer input high width 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,7,8 1,7,8 6 tptin timer input period 3.5v 5.5v 8tpc 8tpc 8tpc 8tpc 1,7,8 1,7,8 7 trtin, tftin timer input rise & fall timer 3.5v 5.5v 100 100 100 100 ns ns 1,7,8 1,7,8 8a twil int. request low time 3.5v 5.5v 100 70 100 70 ns ns 1,2,7,8 1,2,7,8 8b twil int. request low time 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,3,7,8 1,3,7,8 9 twih int. request input high time 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,2,7,8 1,2,7,8 10 twsm stop mode recovery width spec 3.5v 5.5v 12 12 12 12 ns ns 4,8 4,8 11 tost oscillator startup time 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 4,8,9 4,8,9 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p31-p33). 3. interrupt request via port 3 (p30). 4. smr-d5 = 1, por stop mode delay is on. 5. reg. wdtmr. 6. the v cc voltage specification of 5.5v guarantees 5.0v ?.5v and the v cc voltage specification of 3.5v guarantees 3.5v only. 7. smr d1 = 0. 8. maximum frequency for internal system clock is 4 mhz when using low emi osc pcon bit d7 = 0. 9. for rc and lc oscillator, and for oscillator driven by clock driver.
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 22 p r e l i m i n a r y ds97z8x1500 additional timing table (divide-by-one mode) t a = -40 c to +105 c 4 mhz 6 mhz no symbol parameter v cc note [6] min max min max units notes 1 tpc input clock period 4.5v 5.5v 250 250 dc dc 166 166 dc dc ns ns 1,7,8 1,7,8 2 trc,tfc clock input rise & fall times 4.5v 5.5v 25 25 25 25 ns ns 1,7,8 1,7,8 3 twc input clock width 4.5v 5.5v 100 100 100 100 ns ns 1,7,8 1,7,8 4 twtinl timer input low width 4.5v 5.5v 100 70 100 70 ns ns 1,7,8 1,7,8 5 twtinh timer input high width 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,7,8 1,7,8 6 tptin timer input period 4.5v 5.5v 8tpc 8tpc 8tpc 8tpc 1,7,8 1,7,8 7 trtin, tftin timer input rise & fall timer 4.5v 5.5v 100 100 100 100 ns ns 1,7,8 1,7,8 8a twil int. request low time 4.5v 5.5v 100 70 100 70 ns ns 1,2,7,8 1,2,7,8 8b twil int. request low time 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,3,7,8 1,3,7,8 9 twih int. request input high time 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,2,7,8 1,2,7,8 10 twsm stop mode recovery width spec 4.5v 5.5v 12 12 12 12 ns ns 4,8 4,8 11 tost oscillator startup time 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 4,8,9 4,8,9 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p31-p33). 3. interrupt request via port 3 (p30). 4. smr-d5 = 1, por stop mode delay is on. 5. reg. wdtmr. 6. the v cc voltage specification of 5.5v guarantees 5.0v ?.5v and the v cc voltage specification of 3.5v guarantees 3.5v only. 7. smr d1 = 0. 8. maximum frequency for internal system clock is 4 mhz when using low emi osc pcon bit d7 = 0. 9. for rc and lc oscillator, and for oscillator driven by clock driver.
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 23 1 handshake timing diagrams figure 16. input handshake timing data in 1 2 3 4 5 6 /dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid figure 17. output handshake timing data out /dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 24 p r e l i m i n a r y ds97z8x1500 additional timing table (divide by two mode) t a = 0 c to +70 c 12 mhz 4 mhz no symbol parameter v cc note [6] min max min max units conditions notes 1 tpc input clock period 3.5v 5.5v 62.5 62.5 dc dc 250 250 dc dc ns ns 1,7,8 1,7,8 2 trc,tfc clock input rise & fall times 3.5v 5.5v 15 15 25 25 ns ns 1,7,8 1,7,8 3 twc input clock width 3.5v 5.5v 31 31 31 31 ns ns 1,7,8 1,7,8 4 twtinl timer input low width 3.5v 5.5v 70 70 70 70 ns ns 1,7,8 1,7,8 5 twtinh timer input high width 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,7,8 1,7,8 6 tptin timer input period 3.5v 5.5v 8tpc 8tpc 8tpc 8tpc 1,7,8 1,7,8 7 trtin, tftin timer input rise & fall timer 3.5v 5.5v 100 100 100 100 ns ns 1,7,8 1,7,8 8a twil int. request low time 3.5v 5.5v 70 70 70 70 ns ns 1,2,7,8 1,2,7,8 8b twil int. request low time 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,3,7,8 1,3,7,8 9 twih int. request input high time 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,2,7,8 1,2,7,8 10 twsm stop mode recovery width spec 3.5v 5.5v 12 12 12 12 ns ns 4,8 4,8 11 tost oscillator startup time 3.5v 5.5v 5tpc 5tpc 5tpc 5tpc 4,8 4,8 12 twdt watch-dog timer delay time before timeout 3.5v 5.5v 10 5 10 5 ms ms d0 = 0 d1 = 0 5,11 5,11 3.5v 5.5v 20 10 20 10 ms ms d0 = 1 d1 = 0 5,11 5,11 3.5v 5.5v 40 20 40 20 ms ms d0 = 0 d1 = 1 5,11 5,11 3.5v 5.5v 160 80 160 80 ms ms d0 = 1 d1 = 1 5,11 5,11 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p31-p33) 3. interrupt request via port 3 (p30) 4. smr-d5 = 1, por stop mode delay is on 5. reg. wdtmr 6. the v cc voltage specification of 5.5v guarantees 5.0v ?.5v and the v cc voltage specification of 3.5v guarantees 3.5v only. 7. smr d1 = 0 8. maximum frequency for internal system clock is 2 mhz when using low emi osc pcon bit d7 = 0. 9. for rc and lc oscillator, and for oscillator driven by clock driver. 10. standard mode (not low emi output ports) 11. using internal rc
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 25 1 additional timing table (divide by two mode) t a = -40 c to +105 c 12 mhz 4 mhz no symbol parameter v cc note [6] min max min max units conditions notes 1 tpc input clock period 4.5v 5.5v 62.5 62.5 dc dc 250 250 dc dc ns ns 1,7,8 1,7,8 2 trc,tfc clock input rise & fall times 4.5v 5.5v 15 15 25 25 ns ns 1,7,8 1,7,8 3 twc input clock width 4.5v 5.5v 31 31 31 31 ns ns 1,7,8 1,7,8 4 twtinl timer input low width 4.5v 5.5v 70 70 70 70 ns ns 1,7,8 1,7,8 5 twtinh timer input high width 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,7,8 1,7,8 6 tptin timer input period 4.5v 5.5v 8tpc 8tpc 8tpc 8tpc 1,7,8 1,7,8 7 trtin, tftin timer input rise & fall timer 4.5v 5.5v 100 100 100 100 ns ns 1,7,8 1,7,8 8a twil int. request low time 4.5v 5.5v 70 70 70 70 ns ns 1,2,7,8 1,2,7,8 8b twil int. request low time 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,3,7,8 1,3,7,8 9 twih int. request input high time 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 1,2,7,8 1,2,7,8 10 twsm stop mode recovery width spec 4.5v 5.5v 12 12 12 12 ns ns 4,8 4,8 11 tost oscillator startup time 4.5v 5.5v 5tpc 5tpc 5tpc 5tpc 4,8 4,8 12 twdt watch-dog timer delay time before timeout 4.5v 5.5v 5 5 5 5 ms ms d0 = 0 d1 = 0 5,11 5,11 4.5v 5.5v 10 10 10 10 ms ms d0 = 1 d1 = 0 5,11 5,11 4.5v 5.5v 20 20 20 20 ms ms d0 = 0 d1 = 1 5,11 5,11 4.5v 5.5v 80 80 80 80 ms ms d0 = 1 d1 = 1 5,11 5,11 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request via port 3 (p31-p33) 3. interrupt request via port 3 (p30) 4. smr-d5 = 1, por stop mode delay is on 5. reg. wdtmr 6. the v cc voltage specification of 5.5v guarantees 5.0v ?.5v and the v cc voltage specification of 3.5v guarantees 3.5v only. 7. smr d1 = 0 8. maximum frequency for internal system clock is 2 mhz when using low emi osc pcon bit d7 = 0. 9. for rc and lc oscillator, and for oscillator driven by clock driver. 10. standard mode (not low emi output ports) 11. using internal rc
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 26 p r e l i m i n a r y ds97z8x1500 pin functions eprom programming mode d7-d0 data bus. the data can be read from or written to external memory through the data bus. v cc power supply. this pin must supply 5v during the eprom read mode and 6v during other modes. /ce chip enable (active low). this pin is active during eprom read mode, program mode, and program verify mode. /oe output enable (active low). this pin drives the direc- tion of the data bus. when this pin is low, the data bus is output, when high, the data bus is input. epm eprom program mode. this pin controls the differ- ent eprom program mode by applying different voltages. v pp program voltage. this pin supplies the program volt- age. /pgm program mode (active low). when this pin is low, the data is programmed to the eprom through the data bus. clr clear (active high). this pin resets the internal ad- dress counter at the high level. clk address clock. this pin is a clock input. the internal address counter increases by one for each clock cycle. application precaution the production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above v cc occur on pins p31 and /reset. in addition, processor operation of z8 otp devices may be affected by excessive noise surges on the v pp , epm, /oe pins while the microcontroller is in standard mode. recommendations for dampening voltage surges in both test and otp mode include the following: n using a clamping diode to v cc n adding a capacitor to the affected pin n enable eprom/test mode disable otp option bit. standard mode xtal crystal 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc, rc net- work, or external single-phase clock to the on-chip oscilla- tor input. xtal2 crystal 2 (time-based output). this pin connects a parallel-resonant crystal, ceramic resonator, lc, or rc network to the on-chip oscillator output. r//w read/write (output, write low). the r//w signal is low when the ccp is writing to the external program or data memory ( Z86E43/743/e44 only ). /reset reset (input, active low). reset will initialize the mcu. reset is accomplished either through power-on, watch-dog timer reset, stop-mode recovery, or exter- nal reset. during power-on reset and watch-dog timer reset, the internally generated reset drives the reset pin low for the por time. any devices driving the reset line must be open-drain in order to avoid damage from a pos- sible conflict during reset conditions. pull-up is provided in- ternally. after the por time, /reset is a schmitt-trig- gered input. (/reset is available on Z86E43/743/e44 only.) to avoid asynchronous and noisy reset problems, the Z86E43/743/e44 is equipped with a reset filter of four exter- nal clocks (4tpc). if the external reset signal is less than 4tpc in duration, no reset occurs. on the fifth clock after the reset is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. during the reset cycle, /ds is held active low while /as cy- cles at a rate of tpc/2. program execution begins at loca- tion 000ch, 5-10 tpc cycles after /reset is released. for power-on reset, the reset output time is 5 ms. the Z86E43/743/e44 does not reset wdtmr, smr, p2m, and p3m registers on a stop-mode recovery operation. /romless (input, active low). this pin, when connected to gnd, disables the internal rom and forces the device to function as a z86c90/c89 romless z8. (note that, when left unconnected or pulled high to v cc , the device func- tions normally as a z8 rom version). note: when using in rom mode in high emi (noisy) envi- ronment, the romless pins should be connected directly to v cc . /ds (output, active low). data strobe is activated once for each external memory transfer. for a read operation, data must be available prior to the trailing edge of /ds. for write operations, the falling edge of /ds indicates that output data is valid. /as (output, active low). address strobe is pulsed once at the beginning of each machine cycle for external memory transfer. address output is from port 0/port 1 for all exter- nal programs. memory address transfers are valid at the trailing edge of /as. under program control, /as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write.
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 27 1 port 0 (p07-p00). port 0 is an 8-bit, bidirectional, cmos- compatible i/o port. these eight i/o lines can be config- ured under software control as a nibble i/o port, or as an address port for interfacing external memory. the input buffers are schmitt-triggered and nibble programmed. ei- ther nibble output that can be globally programmed as push-pull or open-drain. low emi output buffers can be globally programmed by the software. port 0 can be placed under handshake control. in handshake mode, port 3 lines p32 and p35 are used as handshake control lines. the handshake direction is determined by the configura- tion (input or output) assigned to port 0's upper nibble. the lower nibble must have the same direction as the upper nibble. for external memory references, port 0 provides address bits a11-a8 (lower nibble) or a15-a8 (lower and upper nib- ble) depending on the required address space. if the ad- dress range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for addressing. if one or both nibbles are needed for i/o operation, they must be configured by writing to the port 0 mode register. in romless mode, after a hardware reset, port 0 is configured as address lines a15-a8, and extended timing is set to accommodate slow memory access. the initialization routine can include re- configuration to eliminate this extended timing mode. in rom mode, port 0 is defined as input after reset. port 0 can be set in the high-impedance mode if selected as an address output state, along with port 1 and the con- trol signals /as, /ds, and r//w (figure 18). figure 18. port 0 conguration handshake controls /dav0 and rdy0 (p32 and p35) in 1.5 2.3v hysteresis pad port 0 (i/o) 4 4 oen out open-drain auto latch r 500 k w mcu
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 28 p r e l i m i n a r y ds97z8x1500 pin functions (continued) port 1 (p17-p10). port 1 is an 8-bit, bidirectional, cmos- compatible port with multiplexed address (a7-a0) and data (d7-d0) ports. these eight i/o lines can be pro- grammed as inputs or outputs or can be configured under software control as an address/data port for interfacing external memory. the input buffers are schmitt-triggered and the output buffers can be globally programmed as ei- ther push-pull or open-drain. low emi output buffers can be globally programmed by the software. port 1 can be placed under handshake control. in this configuration, port 3, lines p33 and p34 are used as the handshake controls rdy1 and /dav1 (ready and data available). to inter- face external memory, port 1 must be programmed for the multiplexed address/data mode. if more than 256 external locations are required, port 0 outputs the additional lines (figure 19). port 1 can be placed in the high-impedance state along with port 0, /as, /ds, and r//w, allowing the Z86E43/743/e44 to share common resources in multipro- cessor and dma applications. in rom mode, port 1 is de- fined as input after reset. figure 19. port 1 conguration ( Z86E43/743/e44 only) in 1.5 2.3v hysteresis pad oen out open-drain auto latch r 500 k w port 2 (i/o) handshake controls /dav1 and rdy1 (p33 and p34) mcu
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 29 1 port 2 (p27-p20). port 2 is an 8-bit, bidirectional, cmos- compatible i/o port. these eight i/o lines can be config- ured under software control as an input or output, indepen- dently. all input buffers are schmitt-triggered. bits pro- grammed as outputs can be globally programmed as either push-pull or open-drain. low emi output buffers can be globally programmed by the software. when used as an i/o port, port 2 can be placed under handshake control. af- ter reset, port 2 is defined as an input. in handshake mode, port 3 lines p31 and p36 are used as handshake control lines. the handshake direction is deter- mined by the configuration (input or output) assigned to bit 7 of port 2 (figure 20). figure 20. port 2 conguration oen out in pad port 2 (i/o) handshake controls /dav2 and rdy2 (p31 and p36) mcu auto latch r ? 500 k w open-drain 1.5 2.3v hysteresis
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 30 p r e l i m i n a r y ds97z8x1500 pin functions (continued) port 3 (p37-p30). port 3 is an 8-bit, cmos-compatible port with four fixed inputs (p33-p30) and four fixed outputs (p37-p34). these eight lines can be configured by soft- ware for interrupt and handshake control functions. port 3, pin 0 is schmitt- triggered. p31, p32, and p33 are stan- dard cmos inputs with single trip point (no auto latches) and p34, p35, p36, and p37 are push-pull output lines. low emi output buffers can be globally programmed by the software. two on-board comparators can process an- alog signals on p31 and p32 with reference to the voltage on p33. the analog function is enabled by setting the d1 of port 3 mode register (p3m). the comparator output can be outputted from p34 and p37, respectively, by setting pcon register bit d0 to 1 state. for the interrupt function, p30 and p33 are falling edge triggered interrupt inputs. p31 and p32 can be programmed as falling, rising or both edges triggered interrupt inputs (figure 21). access to counter/timer 1 is made through p31 (t in ) and p36 (t out ). handshake lines for port 0, port 1, and port 2 are also available on port 3 (table 9). note : when enabling or disabling analog mode, the fol- lowing is recommended: 1. allow two nop delays before reading this comparator output. 2. disable global interrupts, switch to analog mode, clear interrupts, and then re-enable interrupts. 3. irq register bits 3 to 0 must be cleared after enabling analog mode. note: p33-p30 differs from the z86c33/c43/233/243 in that there is no clamping diode to v cc due to the eprom high-voltage circuits. exceeding the v ih maximum specification during standard operating mode may cause the device to enter eprom mode.
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 31 1 figure 21. port 3 conguration d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) from stop mode recovery source 1 = analog 0 = digital irq2, tin, p31 data latch irq0, p32 data latch irq1, p33 data latch dig. an. auto latch p30 data latch irq3 port 3 (i/o or control) mcu - + - + p30 r ? 500 k w
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 32 p r e l i m i n a r y ds97z8x1500 pin functions (continued) comparator inputs. port 3, p31, and p32, each have a comparator front end. the comparator reference voltage p33 is common to both comparators. in analog mode, p31 and p32 are the positive input of the comparators and p33 is the reference voltage of the comparators. auto latch. the auto latch puts valid cmos levels on all cmos inputs (except p33-p31) that are not externally driven. whether this level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node, reduces excessive supply current flow in the input buffer. auto latches are available on port 0, port 1, port 2, and p30. there are no auto latches on p31, p32, and p33. low emi emission. the Z86E43/743/e44 can be pro- grammed to operate in a low emi emission mode in the pcon register. the oscillator and all i/o ports can be pro- grammed as low emi emission mode independently. use of this feature results in: n the pre-drivers slew rate reduced to 10 ns typical. n low emi output drivers have resistance of 200 ohms (typical). n low emi oscillator. n internal sclk/tclk= xtal operation limited to a maximum of 4 mhz - 250 ns cycle time, when low emi oscillator is selected. n note for emulation only: do not set the emulator to emulate port 1 in low emi mode. port 1 must always be configured in standard mode. table 9. port 3 pin assignments pin i/o ctc1 analog interrupt p0 hs p1 hs p2 hs ext p30 in irq3 p31 in t in an1 irq2 d/r p32 in an2 irq0 d/r p33 in ref irq1 d/r p34 out an1-out r/d /dm p35 out r/d p36 out t out r/d p37 out an2-out
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 33 1 functional description the mcu incorporates the following special functions to enhance the standard z8 architecture to provide the user with increased design flexibility. reset. the device is reset in one of three ways: 1. power-on reset 2. watch-dog timer 3. stop-mode recovery source note: having the auto power-on reset circuitry built-in, the mcu does not need to be connected to an external power-on reset circuit. the reset time is tpor. the mcu does not re-initialize wdtmr, smr, p2m, and p3m registers to their reset values on a stop-mode recovery operation. note: the device v cc must rise up to the operating v cc specification before the tpor expires. program memory. the mcu can address up to 4/8/16 kb of internal program memory (figure 22). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors that correspond to the six available interrupts. for eprom mode, byte 12 (000ch) to address 4095 (0fffh)/8191 (1fffh)/16384 (3fffh), consists of programmable eprom. after reset, the program counter points at the address 000ch, which is the starting address of the user program. in romless mode, the Z86E43/743/e44 can address up to 64 kb of external program memory. the rom/romless option is only available on the 44-pin devices. figure 22. program memory map 12 11 10 9 8 7 6 5 4 3 2 1 0 external rom and ram location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 on-chip eprom external rom and ram irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 65535 rom mode romless mode 4096/8192/16384 4095/8191/16383 (Z86E43/743/e44 only)
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 34 p r e l i m i n a r y ds97z8x1500 functional description (continued) eprom protect. when in rom protect mode, and exe- cuting out of external program memory, instructions ldc, ldci, lde, and ldei cannot read internal program mem- ory. when in eprom protect mode and executing out of inter- nal program memory, instructions ldc, ldci, lde, and ldei can read internal program memory. data memory (/dm). in rom mode, the Z86E43/743/e44 can address up to 60/56/48 kb of external data memory beginning at location 4096/8192/16384. in romless mode, the Z86E43/743/e44 can address up to 64 kb of data memory. external data memory may be included with, or separated from, the external program memory space. /dm, an optional i/o function that can be programmed to appear on pin p34, is used to distinguish between data and program memory space (figure 23). the state of the /dm signal is controlled by the type of instruction being ex- ecuted. an ldc opcode references program (/dm inac- tive) memory, and an lde instruction references data (/dm active low) memory. figure 23. data memory map 65535 4096/8192/16384 0 external data memory not addressable external data memory eprom romless mode 4095/8191/16383 (Z86E43/743/e44 only)
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 35 1 register file. the register file consists of three i/o port registers, 236/125 general-purpose registers, 15 control and status registers, and three system configuration regis- ters in the expanded register group. the instructions can access registers directly or indirectly through an 8-bit ad- dress field. this allows a short 4-bit register address using the register pointer (figure 24). in the 4-bit mode, the reg- ister file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working-regis- ter group. note: register group e0-ef can only be accessed through working register and indirect addressing modes. expanded register file (erf). the register file has been expanded to allow for additional system control registers, mapping of additional peripheral devices and input/output ports into the register address area. the z8 register ad- dress space r0 through r15 is implemented as 16 groups of 16 registers per group (figure 26). these register banks are known as the expanded register file (erf). the low nibble (d3-d0) of the register pointer (rp) select the active erf bank, and the high nibble (d7-d4) of regis- ter rp select the working register group. three system configuration registers reside in the expanded register file at bank fh: pcon, smr, and wdtmr. the rest of the expanded register is not physically implemented and is reserved for future expansion. figure 24. register pointer register d7 d6 d5 d4 d3 d2 d1 d0 r253 rp expanded register bank working register pointer default after reset = 00h
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 36 p r e l i m i n a r y ds97z8x1500 functional description (continued) figure 25. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register. r3 r2 r1 r0 register group 1 register group 0 r15 to r0 register group f r15 to r4* r3 to r0* ff f0 7f 70 6f 60 5f 50 4f 40 3f 2f 30 20 1f 10 0f 00 * expanded register bank (0) is selected in this figure by handling bits d3 to d0 as "0" in register r253 (rp). ef 80
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 37 1 figure 26. expanded register file architecture 7 6 5 4 3 2 1 0 working register group pointer expanded register group pointer %ff %fo %7f %0f %00 z8 reg. file register pointer % ff % fe % fd % fc % fb % fa % f9 % f8 % f7 % f6 % f5 % f4 % f3 % f2 % f1 % f0 spl rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr 0 0 0 u 0 0 u 0 0 1 u u u u 0 % (f) 0f % (f) 0e % (f) 0d % (f) 0c % (f) 0b % (f) 0a % (f) 09 % (f) 08 % (f) 07 % (f) 06 % (f) 05 % (f) 04 % (f) 03 % (f) 02 % (f) 01 % (f) 00 wdtmr smr 0 0 0 u u 0 u 1 0 1 u u u u 0 0 0 0 u u 0 u 0 0 1 u u u u 0 0 0 0 u u 0 u 0 0 1 u u u u 0 0 0 0 u u 0 u 1 0 1 u u u u 0 0 0 0 u u 0 u 1 0 1 u u u u 0 0 0 0 u u 0 u 0 0 1 u u 0 u 0 0 0 0 u u 0 u 1 0 1 0 u 0 u 0 u u u 0 1 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 u u u u u u u u u u u u u u u u u u u u u u u u u u u u register expanded reg. bank (f) reset condition register expanded reg. bank (0) reset condition register z8 ? standard control registers reset condition % (0) 03 p3 % (0) 02 p2 % (0) 01 p1 % (0) 00 p0 d7 d6 d5 d4 d3 d2 d1 d0 reserved * * * reserved reserved smr2 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pcon 1 1 1 1 1 1 1 0 ? ** u = unknown for romless reset condition: "10110110" * will not be reset with a stop mode recovery ? ** will not be reset with a stop mode recovery, except bit d0. notes: * * sph * uuuuuu 00
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 38 p r e l i m i n a r y ds97z8x1500 functional description (continued) general-purpose registers (gpr). these registers are undefined after the device is powered up. the registers keep their last value after any reset, as long as the reset occurs in the v cc voltage-specified operating range. the register r254 is general-purpose on z86e33/733/e34. r254 and r255 are set to 00h after any reset or stop- mode recovery. ram protect. the upper portion of the ram's address spaces 80h to efh (excluding the control registers) can be protected from reading and writing. this option can be selected during the eprom programming mode. after this option is selected, the user can activate this feature from the internal eprom. d6 of the imr control register (r251) is used to turn off/on the ram protect by loading a 0 or 1, respectively. a "1" in d6 indicates ram protect enabled. stack. the Z86E43/743/e44 external data memory or the internal register file can be used for the stack. the 16-bit stack pointer (r254-r255) is used for the external stack, which can reside anywhere in the data memory for rom- less mode, but only from 4096/8192/16384 to 65535 in rom mode. an 8-bit stack pointer (r255) is used for the internal stack on the z8 that resides within the 236 gener- al-purpose registers (r4-r239). sph (r254) can be used as a general-purpose register when using internal stack only. r254 and r255 are set to 00h after any reset or stop- mode recovery. counter/timers. there are two 8-bit programmable counter/timers (t0 and t1), each driven by its own 6-bit programmable prescaler. the t1 prescaler is driven by in- ternal or external clock sources; however, the t0 prescaler is driven by the internal clock only (figure 27). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (1 to 256), that has been loaded into the counter. when the counter reaches the end of count, a timer interrupt request, irq4 (t0) or irq5 (t1), is generated. the counters can be programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching one (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). the counters, but not the prescalers, can be read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and can be either the internal microprocessor clock divided by four, or an exter- nal signal input through port 3. the timer mode register configures the external timer input (p31) as an external clock, a trigger input that can be retriggerable or non-retrig- gerable, or as a gate input for the internal clock. port 3 line p36 serves as a timer output (t out ) through which t0, t1, or the internal clock can be output. the counter/timers can be cascaded by connecting the t0 output to the input of t1.
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 39 1 figure 27. counter/timer block diagram pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ?16 ? 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register ?2 clock logic irq4 tout p36 irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock d0 (smr) ? ? osc d1 (smr)
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 40 p r e l i m i n a r y ds97z8x1500 functional description (continued) interrupts. the mcu has six different interrupts from six different sources. the interrupts are maskable and priori- tized (figure 28). the six sources are divided as follows: four sources are claimed by port 3 lines p33-p30) and two in counter/timers. the interrupt mask register globally or individually enables or disables the six interrupt requests (table 10). figure 28. interrupt block diagram table 10. interrupt types, sources, and vectors name source vector location comments irq0 /dav0, irq0 0, 1 external (p32), rising/falling edge triggered irq1 irq1 2, 3 external (p33), falling edge triggered irq2 /dav2, irq2, t in 4, 5 external (p31), rising/falling edge triggered irq3 irq3 6, 7 external (p30), falling edge triggered irq4 t0 8, 9 internal irq5 ti 10, 11 internal interrupt edge select irq (d6, d7) irq1, 3, 4, 5 irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 irq2
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 41 1 when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register (ipr). an interrupt machine cycle is activated when an interrupt request is granted. thus, disabling all subsequent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that in- terrupt. all interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 may be rising, falling or both edge trig- gered, and are programmable by the user. the software may poll to identify the state of the pin. programming bits for the interrupt edge select are located in bits d7 and d6 of the irq register (r250). the configuration is shown in table 11. clock. the on-chip oscillator has a high-gain, parallel-res- onant amplifier for connection to a crystal, rc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 10 khz to 16 mhz max, with a series resistance (rs) less than or equal to 100 ohms. the crystal should be connected across xtal1 and xtal2 using the vendor's recommended capacitor values from each pin directly to device pin ground. the rc oscil- lator option can be selected in the programming mode. the rc oscillator configuration must be an external resis- tor connected from xtal1 to xtal2, with a frequency-set- ting capacitor from xtal1 to ground (figure 29). table 11. irq register conguration irq interrupt edge d7 d6 p31 p32 0 0 f f 0 1 f r 1 0 r f 1 1 r/f r/f notes: f = falling edge r = rising edge figure 29. oscillator conguration xtal1 xtal2 c1 c2 c1 c2 c1 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 33 pf typ * f = 8 mhz lc c1, c2 = 22 pf l = 130 ? * f = 3 mhz * rc @ 5v vcc (typ) c1 = 100 pf r = 2k f = 6 mhz external clock l r * typical value including pin parasitics
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 42 p r e l i m i n a r y ds97z8x1500 functional description (continued) power-on reset (por). a timer circuit clocked by a ded- icated on-board rc oscillator is used for the power-on re- set (por) timer function. the por timer allows v cc and the oscillator circuit to stabilize before instruction execu- tion begins. the por timer circuit is a one-shot timer triggered by one of three conditions: 1. power fail to power ok status 2. stop-mode recovery (if d5 of smr=0) 3. wdt time-out the por time is a nominal 5 ms. bit 5 of the stop mode register (smr) determines whether the por timer is by- passed after stop-mode recovery (typical for an external clock and rc/lc oscillators with fast start up times). halt. turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external interrupt irq0, irq1, and irq2 remain active. the device is recovered by interrupts, either externally or internally generated. an in- terrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program con- tinues from the instruction after the halt. in order to enter stop or halt mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. to do this, the user must execute a nop (opcode=ffh) immediately before the appropriate sleep instruction, that is: stop. this instruction turns off the internal clock and ex- ternal crystal oscillation and reduces the standby current to 10 microamperes or less. stop mode is terminated by one of the following resets: either by wdt time-out, por, a stop-mode recovery source, which is defined by the smr register or external reset. this causes the processor to restart the application program at address 000ch. port configuration register (pcon). the pcon regis- ter configures the ports individually; comparator output on port 3, open-drain on port 0 and port 1, low emi on ports 0, 1, 2 and 3, and low emi oscillator. the pcon register is located in the expanded register file at bank f, location 00 (figure 30). ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode figure 30. port conguration register (pcon) (write only) 0 port 0 open drain 1 port 0 push-pull active* d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output 0 port 0 low emi 1 port 0 standard* 0 port 2 low emi 1 port 2 standard* low emi oscillator 0 low emi 1 standard* 0 port 3 low emi 1 port 3 standard* * default setting after reset 0 port 1 open drain 1 port 1 push-pull active* 0 port 1 low emi 1 port 1 standard*
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 43 1 comparator output port 3 (d0). bit 0 controls the com- parator output in port 3. a "1" in this location brings the comparator outputs to p34 and p37, and a "0" releases the port to its standard i/o configuration. the default value is 0. port 1 open-drain (d1). port 1 can be configured as an open-drain by resetting this bit (d1=0) or configured as push-pull active by setting this bit (d1=1). the default val- ue is 1. port 0 open-drain (d2). port 0 can be configured as an open-drain by resetting this bit (d2=0) or configured as push-pull active by setting this bit (d2=1). the default val- ue is 1. low emi port 0 (d3). port 0 can be configured as a low emi port by resetting this bit (d3=0) or configured as a standard port by setting this bit (d3=1). the default value is 1. low emi port 1 (d4). port 1 can be configured as a low emi port by resetting this bit (d4=0) or configured as a standard port by setting this bit (d4=1). the default value is 1. note: the emulator does not support port 1 low emi mode and must be set d4 = 1. low emi port 2 (d5). port 2 can be configured as a low emi port by resetting this bit (d5=0) or configured as a standard port by setting this bit (d5=1). the default value is 1. low emi port 3 (d6). port 3 can be configured as a low emi port by resetting this bit (d6=0) or configured as a standard port by setting this bit (d6=1). the default value is 1. low emi osc (d7). this bit of the pcon register con- trols the low emi noise oscillator. a "1" in this location con- figures the oscillator with standard drive. while a "0" con- figures the oscillator with low noise drive, however, it does not affect the relationship of sclk and xtal. the low emi mode will reduce the drive of the oscillator (osc). the de- fault value is 1. note: 4 mhz is the maximum external clock frequency when running in the low emi oscillator mode. stop-mode recovery register (smr). this register selects the clock divide value and determines the mode of stop-mode recovery (figure 31). all bits are write only except bit 7 which is a read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low or high level is required from the recovery source. bit 5 controls the reset delay after recovery. bits 2, 3, and 4 of the smr register specify the stop-mode recovery source. the smr is located in bank f of the expanded register file at address 0bh.
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 44 p r e l i m i n a r y ds97z8x1500 functional description (continued) figure 31. stop-mode recovery register (write-only except bit d7, which is read-only) d7 d6 d5 d4 d3 d2 d1 d0 smr (f) 0b sclk/tclk divide by 16 0 off 1 on stop mode recovery source 000 por and/or external reset 001 p30 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0:3 111 p2 nor 0:7 stop delay 0 off 1 on stop recovery level 0 low 1 high stop flag 0 por 1 stop recovery * default setting after reset. ** default setting after reset and stop-mode recovery. ** * * * * external clock divide by 2 0 sclk/tclk =xtal/2* 1 sclk/tclk =xtal
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 45 1 sclk/tclk divide-by-16 select (d0). this bit of the smr controls a divide-by-16 prescaler of sclk/tclk. the purpose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). external clock divide-by-two (d1). this bit can elimi- nate the oscillator divide-by-two circuitry. when this bit is 0, the system clock (sclk) and timer clock (tclk) are equal to the external clock frequency divided by two. the sclk/tclk is equal to the external clock frequency when this bit is set (d1=1). using this bit together with d7 of pcon further helps lower emi (i.e., d7 (pcon) = 0, d1 (smr) = 1). the default setting is zero. stop-mode recovery source (d2, d3, and d4). these three bits of the smr register specify the wake up source of the stop-mode recovery (figure 32). table 12 shows the smr source selected with the setting of d2 to d4. p33- p31 cannot be used to wake up from stop mode when programmed as analog inputs. when the stop-mode re- covery sources are selected in this register then smr2 register bits d0, d1 must be set to zero. note: if the port2 pin is configured as an output, this output level will be read by the smr circuitry.. figure 32. stop-mode recovery source p30 p31 p32 p33 p27 stop-mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m) to p33 data latch and irq1 to por reset smr smr smr d4 d3 d2 0 0 1 0 1 0 0 1 1 d4 d3 d2 1 0 0 d4 d3 d2 1 0 1 mux smr smr d4 d3 d2 1 1 0 d4 d3 d2 1 1 1 p20 p23 p20 p27 smr2 smr2 d1 d0 0 1 d1 d0 1 0 p20 p23 p20 p27 smr d4 d3 d2 0 0 0 vdd smr2 d1 d0 0 0 vdd
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 46 p r e l i m i n a r y ds97z8x1500 functional description (continued) stop-mode recovery delay selec t (d5). the 5 ms re- set delay after stop-mode recovery is disabled by pro- gramming this bit to a zero. a "1" in this bit will cause a 5 ms reset delay after stop-mode recovery. the default condition of this bit is 1. if the fast wake up mode is select- ed, the stop-mode recovery source needs to be kept ac- tive for at least 5tpc. stop-mode recovery level select (d6). a "1" in this bit defines that a high level on any one of the recovery sourc- es wakes the mcu from stop mode. a 0 defines low level recovery. the default value is 0. cold or warm start (d7). this bit is set by the device upon entering stop mode. a "0" in this bit indicates that the device has been reset by por (cold). a "1" in this bit indicates the device was awakened by a smr source (warm). stop-mode recovery register 2 (smr2) . this register contains additional stop-mode recovery sources. when the stop-mode recovery sources are selected in this reg- ister then smr register bits d2, d3, and d4 must be 0. watch-dog timer mode register (wdtmr). the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is disabled after pow- er-on reset and initially enabled by executing the wdt in- struction and refreshed on subsequent executions of the wdt instruction. the wdt is driven either by an on-board rc oscillator or an external oscillator from xtal1 pin. the por clock source is selected with bit 4 of the wdt regis- ter. note: execution of the wdt instruction affects the z (ze- ro), s (sign), and v (overflow) flags. wdt time-out period (d0 and d1). bits 0 and 1 control a tap circuit that determines the time-out periods that can be obtained (table 13). the default value of d0 and d1 are 1 and 0, respectively. wdt during halt mode (d2). this bit determines whether or not the wdt is active during halt mode. a "1" indicates that the wdt is active during halt. a "0" dis- ables the wdt in halt mode. the default value is "1". wdt during stop mode (d3). this bit determines whether or not the wdt is active during stop mode. a "1" indicates active during stop. a "0" disables the wdt dur- ing stop mode. this is applicable only when the wdt clock source is the internal rc oscillator. clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscil- lator is bypassed and the por and wdt clock source is driven from the external pin, xtal1, and the wdt is stopped in stop mode. the default configuration of this bit is 0, which selects the rc oscillator. table 12. stop-mode recovery source d4 d3 d2 smr source selection 0 0 0 por recovery only 0 0 1 p30 transition 0 1 0 p31 transition (not in analog mode) 0 1 1 p32 transition (not in analog mode) 1 0 0 p33 transition (not in analog mode) 1 0 1 p27 transition 1 1 0 logical nor of port 2 bits 0-3 1 1 1 logical nor of port 2 bits 0-7 smr:10 operation d1 d0 description of action 0 0 por and/or external reset recovery 0 1 logical and of p20 through p23 1 0 logical and of p20 through p27 table 13. time-out period of wdt d1 d0 time-out of the internal rc osc time-out of the system clock 0 0 5 ms 128 sclk 0 1 10 ms* 256 sclk* 1 0 20 ms 512 sclk 1 1 80 ms 2048 sclk notes: *the default setting is 10 ms.
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 47 1 permanent wdt. when this feature is enabled, the wdt is enabled after reset and will operate in run and halt mode. the control bits in the wdtmr do not affect the wdt operation. if the clock source of the wdt is the inter- nal rc oscillator, then the wdt will run in stop mode. if the clock source of the wdt is the xtal1 pin, then the wdt will not run in stop mode. note: wdt time-out in stop mode will not reset smr,smr2,pcon, wdtmr, p2m, p3m, ports 2 & 3 data registers, but will activate the tpor delay. wdtmr register accessibility. the wdtmr register is accessible only during the first 60 internal system clock cycles from the execution of the first instruction after power-on reset, watch-dog reset or a stop-mode recovery (figures 33 and 34). after this point, the register cannot be modified by any means, intentional or otherwise. the wdtmr cannot be read and is located in bank f of the expanded register file at address location 0fh. clock free wdt reset. the wdt will enable the z8 to reset the i/o pins whenever the wdt times out, even with- out a clock source running on the xtal1 and xtal2 pins. wdtmr bit d4 must be 0 for the clock free wdt to work. the i/o pins will default to their default settings figure 33. watch-dog timer mode register write only d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap int rc osc system clock 00 5 ms 128 sclk 01 10 ms 256 sclk 10 20 ms 512 sclk 11 80 ms 2048 sclk wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved (must be 0) * default setting after reset * * * *
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 48 p r e l i m i n a r y ds97z8x1500 figure 34. resets and wdt clk 18 clock reset generator reset /clear wdt tap select internal rc osc. ck /clr 5ms por 5ms 15ms 25ms 100ms 2v operating voltage det. internal /reset wdt select (wdtmr) clk source select (wdtmr) xtal vdd vlv from stop mode recovery source /wdt stop delay select (smr) + - 4 clock filter wdt/por counter chain m u x /reset
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 49 1 auto reset voltage. an on-board voltage comparator checks that v cc is at the required level to ensure correct operation of the device. reset is globally driven if v cc is below v lv (figure 35). figure 35. typical v lv voltage vs temperature -60 -40 -20 0 20 40 60 80 100 120 140 vcc (volts) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 temperature (?) 3.7
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 50 p r e l i m i n a r y ds97z8x1500 z8 control register diagrams figure 36. port conguration register write only figure 37. stop-mode recovery register write only except bit d7, which is read only 0 port 0 open-drain 1 port 0 push-pull active* d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h comparator output port 3 0 p34, p37 standard* 1 p34, p37 comparator output 0 port 0 low emi 1 port 0 standard* 0 port 2 low emi 1 port 2 standard* low emi oscillator 0 low emi 1 standard* 0 port 3 low emi 1 port 3 standard* * default setting after reset ? must be 1 for z86e33/733/e34 0 port 1 open-drain 1 port 1 push-pull active*? 0 port 1 low emi 1 port 1 standard*? d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0b sclk/tclk divide-by-16 0 off 1 on stop mode recovery source? 000 por only and/or external reset* 001 p30 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on* stop recovery level 0 low* 1 high stop flag 0 por* 1 stop recovery * default setting after reset. ** default setting after reset and stop-mode recovery. external clock divide by 2 0 sclk/tclk =xtal/2* 1 sclk/tclk =xtal ** ? not used in conjunction with smr2 source figure 38. watch-dog timer mode register write only figure 39. stop-mode recovery register 2 write only figure 40. reserved d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap int rc osc system clock 00 5 ms 128 sclk 01 10 ms 256 sclk 10 20 ms 512 sclk 11 80 ms 2048 sclk wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved (must be 0) * default setting after reset * * * * d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) dh note: not used in conjunction with smr source stop-mode recovery source 2 00 por only* 01 and p20,p21,p22,p23 10 and p20,p21,p22,p23,p24, p25,p26,p27 reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) r240
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 51 1 figure 41. timer mode register f1h: read/write figure 42. counter/timer 1 register f2h: read/write d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count* 1 enable t0 count 0 no function* 1 load t0 0 no function* 1 load t1 0 disable t1 count* 1 enable t1 count tin modes 00 external clock input* 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) tout modes 00 not used* 01 t0 out 10 t1 out 11 internal clock out r241 tmr default after reset = 00h d7 d6 d5 d4 d3 d2 d1 d0 t1 initial value (when written) (range: 1-256 decimal 01-00 hex) t1 current value (when read) r242 t1 figure 43. prescaler 1 register f3h: write only figure 44. counter/timer 0 register f4h; read/write figure 45. prescaler 0 register f5h: write only d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass* 1 t1 modulo n clock source 1 t1 internal 0 t1 external timing input (tin mode) prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 *default after reset d7 d6 d5 d4 d3 d2 d1 d0 t0 initial value (when written) (range: 1-256 decimal 01-00 hex) t0 current value (when read) r244 t0 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n reserved (must be 0) r245 pre0 prescaler modulo (range: 1-64 decimal 01-00 hex)
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 52 p r e l i m i n a r y ds97z8x1500 z8 control register diagrams (continued) figure 46. port 2 mode register f6h: write only figure 47. port 3 mode register f7h: write only d7 d6 d5 d4 d3 d2 d1 d0 p20 - p27 i/o definition 0 defines bit as output 1 defines bit as input* r246 p2m * default after reset d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 open-drain 1 port 2 push-pull active reserved (must be 0) 0 p32 = input p35 = output 1 p32 = /dav0/rdy0 p35 = rdy0//dav0 00 p33 = input p34 = output 01 p33 = input 10 p34 = /dm 11 p33 = /dav1/rdy1 p34 = rdy1//dav1 0 p31 = input (tin) p36 = output (tout) 1 p31 = /dav2/rdy2 p36 = rdy2//dav2 0 p30 = input p37 = output 0 p31, p32 digital mode 1 p31, p32 analog mode default after reset = 00h ? z86e33/733/e34 must be 00 ? figure 48. port 0 and 1 mode register f8h: write only figure 49. interrupt priority register f9h: write only d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p03 - p00 mode 00 output 01 input 1x a11 - a8 stack selection 0 external 1 internal* p17 - p10 mode 00 byte output? 01 byte input* 10 ad7 - ad0 11 high-impedance ad7 - ad0, /as, /ds, /r//w, a11 - a8, a15 - a12, if selected p07 - p04 mode 00 output 01 input* 1x a15 - a12 external memory timing 0 normal* 1 extended reset condition = 0100 1101b for romless condition = 1011 0110b ? z86e33/733/e34 must be 00 * * default after reset d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 reserved (must be 0) r249 ipr
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 53 1 figure 50. interrupt request register fah: read/write figure 51. interrupt mask register fbh: read/write figure 52. flag register fch: read/write d7 d6 d5 d4 d3 d2 d1 d0 r250 irq inter edge p31 p32 = 00 p31 p32 - = 01 p31 - p32 = 10 p31 - p32 - = 11 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = p30 input irq4 = t0 irq5 = t1 default after reset = 00h d7 d6 d5 d4 d3 d2 d1 d0 1 enables ram protect ? 1 enables irq5-irq0 (d0 = irq0) 1 enables interrupts r251 imr ? this option must be selected when rom code is submitted for rom masking, otherwise this control bit is disabled permanently. d7 d6 d5 d4 d3 d2 d1 d0 r252 flags user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag figure 53. register pointer fdh: read/write figure 54. stack pointer high feh: read/write figure 55. stack pointer low ffh: read/write d7 d6 d5 d4 d3 d2 d1 d0 r253 rp expanded register bank working register pointer default after reset = 00h d7 d6 d5 d4 d3 d2 d1 d0 (Z86E43/743/e44) stack pointer upper byte (sp8 - sp15) r254 sph (z86e33/733/e34) 0 = 0 state 1 = 1 state default after reset = 00h d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp0 - sp7) r255 spl default after reset = 00h
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 54 p r e l i m i n a r y ds97z8x1500 package information figure 56. 40-pin dip package diagram figure 57. 44-pin plcc package diagram
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 55 1 figure 58. 44-pin qfp package diagram figure 59. 28-pin dip package diagram
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 56 p r e l i m i n a r y ds97z8x1500 package information (continued) figure 60. 28-pin soic package diagram figure 61. 28-pin plcc package diagram
z86e33/733/e34/e43/743/e44 zilog cmos z8 otp microcontrollers ds97z8x1500 p r e l i m i n a r y 57 1 ordering information Z86E43/743/e44 (12 mhz) for fast results, contact your local zilog sales office for assistance in ordering the part desired. package p = plastic dip v = plastic chip carrier f = plastic quad flat pack s = soic (small outline integrated circuit) temperature s = 0 c to +70 c e = -40 c to +105 c speed 12 = 12 mhz environmental c = plastic standard 40-pin dip 44-pin plcc 44-pin qfp Z86E4312psc Z86E4312vsc Z86E4312fsc Z86E4312pec Z86E4312vec Z86E4312fec z8674312psc z8674312vsc z8674312fsc z8674312pec z8674312vec z8674312fec z86e4412psc z86e4412vsc z86e4412fsc z86e4412pec z86e4412vec z86e4412fec z86e33/733/e34 (12 mhz) 28-pin dip 28-pin soic 28-pin plcc z86e3312psc z86e3312ssc z86e3312vsc z86e3312pec z86e3312sec z86e3312vec z8673312psc z8673312ssc z8673312vsc z8673312pec z8673312sec z8673312vec z86e3412psc z86e3412ssc z86e3412vsc z86e3412pec z86e3412sec z86e3412vec example: z 86e43 12 p s c is a z8e43, 12 mhz, dip, 0?to +70?, plastic standard flow environmental flow temperature package speed product number zilog prex
z86e33/733/e34/e43/743/e44 cmos z8 otp microcontrollers zilog 58 p r e l i m i n a r y ds97z8x1500 ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com

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